![verilog HDLBits刷题[Latches and Flip-Flops]“Edgedetect”---Detect an edge（边沿检测）](http://pic.xiahunao.cn/yaotu/verilog HDLBits刷题[Latches and Flip-Flops]“Edgedetect”---Detect an edge（边沿检测）)
一、题目For each bit in an 8-bit vector, detect when the input signal changes from 0 in one clock cycle to 1 the next (similar to positive edge detection). The output bit should be set the cycle after a 0 to 1 transition occurs.Here are some examples. For clarity, in[1] and pedge[1] are shown separately.Module Declarationmodule top_module ( input clk, input [7:0] in, output [7:0] pedge );二、分析输入的某一位从0变为1时对应一个上升沿。可先对输入进行打一拍相当于将数据向右移动一个时钟周期当移动前为1移动后为0可判断数据在某个时钟延出现上升沿。画出每个变量的时序便可理解。三、代码实现注意的结果是一位~是按位取反module top_module ( input clk, input [7:0] in, output [7:0] pedge ); reg [7:0]in_1; wire [7:0]pedge_temp; always(posedge clk) in_1in; assign pedge_tempin(~in_1); always(posedge clk) pedgepedge_temp; endmodulemodule top_module ( input clk, input [7:0] in, output [7:0] pedge ); reg [7:0]in_1; always(posedge clk) in_1in; integer i; always(posedge clk) for(i0;i8;ii1) if(in[i](~in_1[i])) pedge[i]1; else pedge[i]0; endmodule 或者 module top_module ( input clk, input [7:0] in, output [7:0] pedge ); wire [7:0]in_1; always(posedge clk)begin in_1in; end always(posedge clk)begin for(int i0;i7;i)begin if ((in[i]1b1)(in_1[i]1b0)) pedge[i]1b1; else pedge[i]1b0; end end endmodule四、时序
一、题目For each bit in an 8-bit vector, detect when the input signal changes from 0 in one clock cycle to 1 the next (similar to positive edge detection). The output bit should be set the cycle after a 0 to 1 transition occurs.Here are some examples. For clarity, in[1] and pedge[1] are shown separately.Module Declarationmodule top_module ( input clk, input [7:0] in, output [7:0] pedge );二、分析输入的某一位从0变为1时对应一个上升沿。可先对输入进行打一拍相当于将数据向右移动一个时钟周期当移动前为1移动后为0可判断数据在某个时钟延出现上升沿。画出每个变量的时序便可理解。三、代码实现注意的结果是一位~是按位取反module top_module ( input clk, input [7:0] in, output [7:0] pedge ); reg [7:0]in_1; wire [7:0]pedge_temp; always(posedge clk) in_1in; assign pedge_tempin(~in_1); always(posedge clk) pedgepedge_temp; endmodulemodule top_module ( input clk, input [7:0] in, output [7:0] pedge ); reg [7:0]in_1; always(posedge clk) in_1in; integer i; always(posedge clk) for(i0;i8;ii1) if(in[i](~in_1[i])) pedge[i]1; else pedge[i]0; endmodule 或者 module top_module ( input clk, input [7:0] in, output [7:0] pedge ); wire [7:0]in_1; always(posedge clk)begin in_1in; end always(posedge clk)begin for(int i0;i7;i)begin if ((in[i]1b1)(in_1[i]1b0)) pedge[i]1b1; else pedge[i]1b0; end end endmodule四、时序
