![verilog HDLBits刷题[Finite State Machines]“Fsm3s”---Simple FSM 3 （synchronous reset）](http://pic.xiahunao.cn/yaotu/verilog HDLBits刷题[Finite State Machines]“Fsm3s”---Simple FSM 3 （synchronous reset）)
1、题目See also: State transition logic for this FSMThe following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include a synchronous reset that resets the FSM to state A. (This is the same problem as Fsm3 but with a synchronous reset.)StateNext stateOutputin0in1AAB0BCB0CAD0DCB12、代码module top_module( input clk, input in, input reset, output out); // reg [3:0] state,next_state; parameter A0, B1, C2, D3; // State transition logic: Derive an equation for each state flip-flop. assign next_state[A] state[0](~in) | state[2](~in); assign next_state[B] state[0](in) | state[1](in)|state[3](in); assign next_state[C] state[1](~in) | state[3](~in); assign next_state[D] state[2](in); always (posedge clk)begin if(reset) state4d1; else statenext_state; end // Output logic: assign out (state[D]1b1); endmodule3、结果
1、题目See also: State transition logic for this FSMThe following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include a synchronous reset that resets the FSM to state A. (This is the same problem as Fsm3 but with a synchronous reset.)StateNext stateOutputin0in1AAB0BCB0CAD0DCB12、代码module top_module( input clk, input in, input reset, output out); // reg [3:0] state,next_state; parameter A0, B1, C2, D3; // State transition logic: Derive an equation for each state flip-flop. assign next_state[A] state[0](~in) | state[2](~in); assign next_state[B] state[0](in) | state[1](in)|state[3](in); assign next_state[C] state[1](~in) | state[3](~in); assign next_state[D] state[2](in); always (posedge clk)begin if(reset) state4d1; else statenext_state; end // Output logic: assign out (state[D]1b1); endmodule3、结果
