![verilog HDLBits刷题[Finite State Machines]“Exams/m2014 q6c”---Q6c:FSM one-hot next-state logic](http://pic.xiahunao.cn/yaotu/verilog HDLBits刷题[Finite State Machines]“Exams/m2014 q6c”---Q6c:FSM one-hot next-state logic)
1、题目Consider the state machine shown below, which has one inputwand one outputz.For this part, assume that a one-hot code is used with the state assignment y[6:1] 000001, 000010, 000100, 001000, 010000, 100000 for states A, B,..., F, respectively.Write a logic expression for the next-state signals Y2 and Y4. (Derive the logic equations by inspection assuming a one-hot encoding. The testbench will test with non-one hot inputs to make sure youre not trying to do something more complicated).2、分析独热码只有一bit为1其它全为0。从A-F,即从next_state[1]-next_state[6]。拿A来说从别的状态到状态A只有两种情况A-A和D-A。对于B只有A能到B状态。3、代码module top_module ( input [6:1] y, input w, output Y2, output Y4); parameter A6b000001,B6b000010,C6b000100,D6b001000,E6b010000,F6b100000; reg [6:1]next_state; assign next_state[1]y[1]w||y[4]w; assign next_state[2]y[1](!w); assign next_state[3]y[2](!w)||y[6](!w); assign next_state[4]y[2]w||y[3]w||y[5]w||y[6]w; assign next_state[5]y[3](!w)||y[5](!w); assign next_state[6]y[4](!w); assign Y2next_state[2]; assign Y4next_state[4]; endmodule
1、题目Consider the state machine shown below, which has one inputwand one outputz.For this part, assume that a one-hot code is used with the state assignment y[6:1] 000001, 000010, 000100, 001000, 010000, 100000 for states A, B,..., F, respectively.Write a logic expression for the next-state signals Y2 and Y4. (Derive the logic equations by inspection assuming a one-hot encoding. The testbench will test with non-one hot inputs to make sure youre not trying to do something more complicated).2、分析独热码只有一bit为1其它全为0。从A-F,即从next_state[1]-next_state[6]。拿A来说从别的状态到状态A只有两种情况A-A和D-A。对于B只有A能到B状态。3、代码module top_module ( input [6:1] y, input w, output Y2, output Y4); parameter A6b000001,B6b000010,C6b000100,D6b001000,E6b010000,F6b100000; reg [6:1]next_state; assign next_state[1]y[1]w||y[4]w; assign next_state[2]y[1](!w); assign next_state[3]y[2](!w)||y[6](!w); assign next_state[4]y[2]w||y[3]w||y[5]w||y[6]w; assign next_state[5]y[3](!w)||y[5](!w); assign next_state[6]y[4](!w); assign Y2next_state[2]; assign Y4next_state[4]; endmodule
