![verilog HDLBits刷题[Bulid a circuit from a simulation waveform]“Sim/circuit5”---Combinational circuit5](http://pic.xiahunao.cn/yaotu/verilog HDLBits刷题[Bulid a circuit from a simulation waveform]“Sim/circuit5”---Combinational circuit5)
1、题目2、分析当c为大于等于4时q为fc0qbc1qec2qac3qd相当于多路选择器3、代码module top_module ( input [3:0] a, input [3:0] b, input [3:0] c, input [3:0] d, input [3:0] e, output reg [3:0] q ); always (*) begin case (c) 0 : q b; 1 : q e; 2 : q a; 3 : q d; default : q 4hf; endcase end endmodule4、结果
1、题目2、分析当c为大于等于4时q为fc0qbc1qec2qac3qd相当于多路选择器3、代码module top_module ( input [3:0] a, input [3:0] b, input [3:0] c, input [3:0] d, input [3:0] e, output reg [3:0] q ); always (*) begin case (c) 0 : q b; 1 : q e; 2 : q a; 3 : q d; default : q 4hf; endcase end endmodule4、结果
